Rectangular-code regenerator



May- 27, 1969 RECTANGULAR- CODE REGENERATOR SUKEHIRO ITO ET AL.

nvenlor S11-o @Hokwma sheet Z of 5 May 27, 1969 sUKEHlRo |To ET AL.

RECTANGULAR-CODE REGENERATOR :filed July 22, 1964 8.1m swxcmm Attorney May 27, 1969 RECTANGULAR- CODE REGENRATOR Filed July 22, 1964 sheet @f5 l f7 /VI\/Vk l n U \U/ \U/\Tf2 H H j n U n U U Pff/M U U U V Tf1/e2 Umunuu Uuffg Inventor' y SITO SDHUAMA By" A Harney su'Kf-:Hlo |To ETAL 3,447,086 l SUKEHIRO ITO ET AL RECTANGULAR-CODE REGENERATOR May 27,1969

Sheet Filed July 22. 1964 Inventor Siro SWOKMAMA By A Horne y Sheet Filed July 22. 1964 Attorney i United States Patent O 3,447,086 RECTANGULAR-CODE REGENERATOR Sukehiro Ito and Seijiro Yokoyama, Tokyo, Japan, as-

signors to Nippon Electric Company, Limited, Tokyo,

Japan, a corporation of Japan Filed July 22, 1964, Ser. No. 384,493 Claims priority, application Japan, July 29, 1963, 38/39,987 Int. Cl. H04b J/10; H041 15/24 U.S. Cl. 325--323 12 Claims ABSTRACT F THE DISCLOSURE This invention relates to a code regenerator for demodulating and regenerating a received wave which has been modulated by one or more rectangular code trains.

The rectangular-code regenerator of this invention includes: a clock frequency detector responsive to a modulated wave modulated by at least a train of rectangular codes for producing a clock pulse lseries having a recurrence period equal to the duration of an elementary code constituting the rectangular code train; demodulating and separating means responsive to said clock pulse series and the modulated Wave for producing ('with reference to the time position of the elementary codes constituting the rectangular code train contained in the modulated wave) a predetermined number of Ipartial demodulated code trains which are demodulated and separated from one another. The separation is performed in such a manner that only one of the elementary codes may be present (in accordance with the sequence of successive time intervals determined by the clock pulse series) within each of the time periods, each consisting of the predetermined number of the time intervals. Integrating circuits are also provided and each is responsive to one of the partial demodulated code trains and the clock pulse series for integrating (within the preceding one of any Successive two of the time periods) the value of the one of said partial demodulated code trains. This integration produces an integrated value which is discharged in the succeeding time period (and before the integration substantially takes place within the succeeding one of the successive two time periods) to produce an integrated value train having one integrated value, for each of the time periods. Reading-out circuits are also provided, each of lwhich is responsive to one of the integrated value trains and the clock pulse series for reading out the integrated values (before the discharging of the integrated value to be read out substantially takes place) to produce a partial read-out value train consisting of read-out values each representing the read-out integrated value. A combining circuit is also provided, which is responsive to a plurality of the partial read-out value trains for producing a readout value train corresponding to the rectangular code train. A shaping circuit responsive to the read-out signal train produces the replica of said rectangular code train. The modulated wave may be either amplitude-modulated, frequency-modulated, or phase-modulated signals.

'In a multichannel'telephone communication system 3,447,086 Patented May 27, 1969 ICC (wherein information is quantized, converted into digital signals, and transmitted on a carrier wave which is modulated by digital signals and, in which on the receiver side, the digital lsignals are detected in the modulated wave and returned to the initial information or in a telegraph communication system wherein the carrier wave is modulated by the information which by itself is in the form of digital signals) it is desirable to reduce as far as possible, disturbances to the detected digital signals caused by noise which increases to relatively large values ywith decreases of the carrier wave input level. In order to extract the signal from a combination of signal and noise (with the disturbance of the noise reduced to a minimum) it suiiices to make the weighting function of the filter used be equal to the waveform of the signal. In other Words, the use of a matched lilter is required whose transfer function is given by the complementary imaginary number of the spectrum of the signal. If the signal to be recovered is a rectangular binary-code train, the matched filter for the rectangular binary-code train may be obtained (as is already known in principle) by arranging the filter so that each of the elementary codes constituting the rectangular binary-code train can be integrated within the whole duration T of the sampled elementary code without any influence on the remaining elementary codes. Moreover, the results of integration should be read out to determine the state or condition of the concerned elementary code. Furthermore, these processes should be successively repeated for each elementary code. In order to realize such an ideal matched filter for a rectangular binary-code train, it is necessary to reduce (so as to be completely negligibly short as compared with the duration T of the elementary code) the sum of the time required for reading out the result of integration of one of the elementary codes and the time needed for discharging the result of integration, down to a predetermined level, thereby to prepare for the integration of the succeeding elementary code. The time demanded for reading-out and discharging, however, is dependent on the speed and ability of the circuit elements and for example may not be shorter than 0.1 microsecond. Consequently, with this assumption the duration T of an elementary code (|which must be suliiciently longer than and for example may be ten times, as long as this 0.1 microsecond) can not be shorter than 1 microsecond. This means that the transmission speed can never be raised above one megabit per second. It becomes difficult therefore to detect by means-of a matched dilter, high-speed codes, such as pulse code modulated multichannel telephone signals. In this connection, the conventional method of reception which is widely adopted, is to allow the code train containing the noise to rpass through a low-pass Ifilter, to read out successively the values of the elementary codes at the proximity of their respective centers, and to recover the code train by shaping. With this method, the low-pass filter serves to reduce the noise. nIt is, however, impossible to make such a low-pass filter a matched iilter. Furthermore, the low-pass filter causes interference among the codes. Therefore, this means th'at the disturbance caused by the noise is far greater with a low-pass filter than with an ideal matched filter.

An object of this invention is to provide a high speed code regenerator having an ideal matched [filter circuit.

Another object of this invention is to provide a code regenerator having an ideal matched filter circuit in which the read out discharge time may be regarded as being substantially zero.

Still another object of this invention is to provide a code regenerator which is capable of substantially unrestricted transmission speeds.

Another object of the invention is therefore to provide an ideal matched filter circuit which produces low noise among the codes and wherein the read-out and discharge time maybe regarded to be substantially zero.

The above-mentioned and other features and objects of this invention and means for attaining them will become more apparent and the invention itself `will be best under stood by reference to the following description of embodiments of the invention taken in conjunction with the accompanying' drawings in which:

FIG. 1 is a block diagram of a matched filter according to this invention;

FIGS. 2-5 are waveforms for explaining the operation of the filter of FIG. 1, and plots of time on the abscissa axis vs. amplitude on the ordinate axis;

FIG. 6 is a block diagram of an embodiment of an invention which is adapted for two-phase phase modulation;

FIGS. 7-18 are waveforms for explaining the operation of the embodiment of FIG. 6 and are plots of time on the abscissa axis vs. amplitude on the ordinate axis;

FIG. 19 is a block diagram of another embodiment of the invention;

FIG. 20 is a block diagram of still another embodiment of the invention which is adapted to four-phase phase modulation', and

FIG. 2l is a block diagram of still another embodiment of the invention.

Referring to FIG. 1, a matched filter is shown which includes a terminal for receiving the signal P and noise N; an integrating circuit 31, an integrated value readingout circuit 32, and a shaping circuit 33. As shown in FIG. 2, a received and demodulated rectangular binary-code train P containing the noise N is composed of a number of elementary codes, each of which has a duration T (as shown above elementary code 34). The integrating circuit 31 integrates the voltage value of each of the elementary codes for the time during which the elementary code is present. FIG. 3 shows a series I of the thus obtained integrated values. The read-out circuit 32 derives from the integrated value a series of read-out value 1R shown in FIG. 4. As shown in FIG. 4, a pulse may be derived whenever a zero point occurs in FIG. 3. The shaping circuit 33 transforms the read-out values into the shaped rectangular Ibinary-code train PM shown in FIG. 5.

To explain the function by which the circuit shown in FIG. 1 serves as a matched filter for a rectangular `binarycode train, let it -be assumed that an arbitrary elementary code P0 illustrated by 34 of FIG. 2 alone is to be detected among the elementary codes of a rectangular binary-code train P shown in FIG. 2 and that the duration of the elementary code P0 is from a time t 0-T/ 2 to another time I n-i-T/Z. Then, the elementary code P0 is integrated at the integrating circuit 31 for the duration from t 0-T/2 to I O-l-T/Z and thus an integrated value I0 is obtained vIf the spectrum of the elementary code Po is S(jp), the elementary code P0 is given by the Fourier integral or by Adan-flac@ exp. @mdp (2) where p is the angular frequency and j represents the imaginary unit. By substituting Equation 2 into Equation 1, we obtain:

(4) Equation 4 shows that the value I0 derived through integration of the elementary code P0 from the time f U-T/Z to the time f O-l- T/ 2 is equal to the value which would be obtained `by causing the elementary code P0 t0 pass through a filter whose transfer function is sin 11T/2 and then reading out the same at the center time point f o of the elementary code P0.,On the other hand, it is already known that the frequency characteristic of a generally rectangular pulse is given by the same 4formula as Equation 5. Therefore the spectrum S(ip) of the elementary code P0 (which is a rectangular pulse) is of the same frequency characteristic as the transfer function given by the Expression 5. As a result, the circuit of FIG. 1 serves as a matched filter for the rectangular binary-code train.

Now that the theoretical aspects have been clarified concerning the realization of a matched filter for a rectangular binary-code train, the invention for embodying such an ideal matched filter will be explained with further reference to the drawings.

Referring to FIG. 6 a block diagram is indicated of an embodiment of this invention for two-phase, phase demodulation. The modulated wave has been two-phase phase `modulated by a rectangular binary-code train to derive the replica of the original rectangular binary code train. The `modulated wave which has been two-phase phase modulated by a rectangular binary-code train is supplied from an input terminal 3S connected to input signal source 210. The input signal is supplied to a twophase phase demodulator 36 to be demodulated into a demodulated rectangular binary-code train P having superimposed noise N. P and N together have the wave shape shown in FIG. 2. A portion of the demodulated rectangular binary-code train P is supplied to a frequency detector 37 which detects the frequency B which is equal to the reciprocal of the duration T of an elementary code and produces clock pulse output signals PC having the clock frequency B of the rectangular binary code train. The clock pulse series Pc drives both the .gate control signal generator 3S (which may be a flip-op circuit) and a pulse generator 39. The output PG of the gate control signal generator 38 is a rectangular wave which alternatingly assumes, as shown in FIG. 8, two different voltages E1 and E2 during each interval T of an elementary code of the demodulated rectangular binary-code train P. The output PG serves to control transmission gates G1 (41) and G2 (42) for governingtransmission of the demodulated rectangular binary-code train P and other gates G3 (43), G4 (44), G5 (45) and G6 (46) for conditioning two signal paths which will be explained hereinafter. The two outputs obtained at the respective output terminals of the pulse generator 39 are two pulse trains consisting of pulses whose duration AT is shorter than half of the duration T of an-elementary code. One of the outputs from generator 39, PR, is phase-synchronized, as shown in FIG. 9, with the demodulated rectangular binary-code train P. The train PR is a read-out pulse series which is connected through read-out pulse gates 43 and 44 to control read-out circuits 61 and 62 which read out integrated values obtained at integrating circuits 51 and 52, respectively. The other output PD of generator 39, as shown in FIG. lO, lags behind the readout pulse series PR by the duration AT. The series PD acts as a discharging pulse series which controls through the discharging pulse gates 45 and `46 the discharge of the above-mentioned integrated values.

Now description will be made 0f the manner in which the demodulated rectangular binary-code train P, obtained at the two-phase phase demodulator 36, is successively modified by various pulse signals at the gates, integrating circuits, and reading-out circuits. Gates G1 (41) and G2 (42) alternatingly intermittently allows the demodulated rectangular binary-code train P to pass therethrough. More particularly when the gate control signal PG assumes the voltage E1, the gate G1 (41) is open and the gate G2 (42) is closed. When the gate control signal PG assumes the value E2, gate G1 is closed and gate `G2 is open. FIG. l1 shows with reference to the gate control signal PG illustrated in FIG. 8 the gate number of that gate which is opened. It follows, therefore, that every other one of these elementary codes of the demodulated rectangular binary-code train P supplied to both of the gates G1 and G2 are alternately extracted as shown in FIG. 12. Thus, demodulated rectangular binary-code train P is divided into two partial demodulated rectangular binary-code trains, each of whose duty factor is 50%. In other words, first and second parallel rectangular binary-code train P(G1) and P'(G2) of FIG. 12 are thus generated.

In order to explain the operation of the gates G3 (43) and G4 (44) which select the reading-out pulse series PR and the gates G5 (45) and G5 (46) which select the discharging pulse series PD reference will lbe made now to FIG. 13. The gates G3 (43) and G5 (45) are closed and the gates G4 (44) and G5 (46) are opened when the gate control signal PG assumes the voltage El. When the gate control signal PG assumes the value o'f E2, the gates G3 (43) and G5 (45) are open and the gates G4 (44) and G6 (46) are closed. FIG. 13 indicates sequentially the number of gates which are open. When FIG. 13 is considered in conjunction with FIG. 9, illustrating the read-out pulse series PR and FIG. illustrating the discharging pulse series PD, it is evident that a first read-out pulse series PR(G3) and a first discharging pulse series PD(G5) shown in FIG. 14 are supplied respectively through the gates G3 (43) and G5 (45) to the read-out circuit 61 and to the integrating circuit 51. Likewise, a second reading-out pulse series PR(G4) and a second discharging pulse series PD(G5) illustrated in FIG. 15 are applied through the gate G4 (44) to the reading-out circuit 62 and through the gate G5 (46) to the integrating `circuit 52, respectively.

Proceeding with the explanation of FIG. 6, the effect caused on the first parallel rectangular binary-code train P(G1) (of the two parallel rectangular binary-code trains shown in FIG. l2) will now be examined. When the gate control signal PG assumes the voltage El and the gate G1 (41) is consequently open, then the integrating circuit 51 integrates the code train P(G1) to derive first integrated values I1 which are shown in FIG. 16 by the substantially triangular portions on the left-hand sides of the waveforms. One such portion is indicated by the reference numeral 211. During these time periods, the gates G3 (43) and G5 (45) are closed. When the gate control signal assumes the value E2 the gate G1 (41) is closed and the function of the integrating circuit 51 ceases. As a result, the first integrated value I1 become constant in the manner illustrated in FIG. 16 by the intermediate slant rectangular portions. One such intermediate portion is indicated at 212. When gate G3 (43) opens,the -rst read-out pulse series PR(G3) shown in FIG. 14 drives the read-out circuit 61 to read out the first integrated values I1. As soon as this read-out ends, the first discharging pulse PD(G5) of the duration AT also shown in FIG. 14, passes through the .previously opened gate G5 (45) to discharge the first integrated values I1 in the manner shown in FIG. 16I by the right-hand side small triangles (for example 213) to reset the integrating circuit 51 to the original state from which the integration started. By cycling of the integration, reading-out, and discharging operation, the first parallel read-out values Im illustrated in FIG. 17 are supplied to a combining circuit 71 one after another. The operation of integrator 52 and read-out circuit 62 in conjunction with the other rectangular binary pulse train P(G2) is similar to that of integrator 51 and read-out circuit '61.

The second parallel rectangular binary-code train P(G2) is supplied to integrator 52. The opening and closing of the six gates G1-G5 by the gate control signal PG is performed in the manner shown in FIGS. l1 and 13. The shapes and phases of the second read-out pulse series PR(G4) supplied through the gate G4 (44) to the read-out Circuit 62 and the second discharging pulse series PD(G6) supplied through the gate G5 (46 to the integrating circuit 52 (the pulse.r series are shown in FIG. 15) are the same as explained in conjunction with the first parallel rectangular binary-code train P(G1). Therefore, the second integrated values I2 are second binary rectangular pulse trains shown in FIG. 16. The second parallel read-out values IR2 are illustrated in FIG. 17.

The first and the second read-out values IRI and IRZ are both supplied to the combining circuit 71 where they are combined to become the read-out value train IR, shown in FIG. 18 which is restored at a shaping circuit 81 to a shaped rectangular binary-code train PM whose form is similar to the original rectangular binary-code train shown in FIG. 5. The output of said shaping circuit is supplied to utilization circuit 211.

As will lbe understood from the foregoing, the rectangular code regenerator for the embodiment divides the input signal into two parallel rectangular binary-code trains alternatingly on a time basis of an elementary code. Reading-out and discharging of an integrated value are performed in that -blank time interval during the duration of an elementary `code which follows the integration of an elementary `code in each of the `binary-code trains. This arrangement provides a resulting characteristic which is substantially the same as the aforementioned ideal matched filter having a zero read-out and discharge time interval.

Referring now to FIG. 19, there is illustrated therein another embodiment of a rectangular binary-code regenerator according to this invention and which is also used in conjunction with a two-phase phase demodulator. This embodiment is nearly the same as that of the embodiment shown in FIG. 6, except that gates G1 (101) and G2 (102) of FIG. 19 (which correspond to the gates G1 (41) and G2 (42) shown in FIG. 6) do not transmit the demodulated rectangular' binary-code train therethrough but rather transmits the modulated wave itself. The modulated wave is not formed in two partial or parallel rectangular binary-code trains until the partial modulated waves are demodulated at phase demodulators 111 and 112. The feature of this embodiment resides in the fact that the construction and adjustment of the gates G1 (101) and G2 (102) are very simple as compared with those of the gates G1 (41) and G2 (42) shown in FIG. 6 because it is unnecessary for the former to transmit direct-current components. In other respects the operation of FIG. 19 is similar to that of the embodiment of FIG. 6.

In the description of the embodiment of FIGS. 6 and 19, it has been the underlying assumption that the time required for reading-out and discharging is shorter than the duration T of an elementary code. If the transmission speed is so great that the time for reading-out and discharging is longer than the duration T of an elementary code at that time, it is only necessary to divide the demodulated rectangular binary-code train into three or more parallel rectangular binary-code trains. If division into three is desired, it is possible to achieve the same operation as has been described, by replacing the gate control signal generator 38 shown in FIG. 6 for producing two voltages E1 and E2, with a gate control signal generator (not shown) for producing three voltages El, E2, and E3 and by arranging besides the series comprising the gate G1 (41), integrating circuit 51, and reading-out circuit 61, two additional and similar series.

In the foregoing explanation, the input signal has been a two-phase phase-modulated wave. A similar rectangular binary-code regenerator may be obtained even if the inp'ut Wave is four-phase phase-modulated.

Referring to FIG. 20, there is illustrated therein a fourphase phase-modulator 121 which is connected to the input signal source 210 and provides at one of its two output terminals a first demodulated rectangular binary-code train P1 which includes the first and third phases of the four phases and which are separated by from each other. At the other output terminal of demodulator 121, a second demodulated rectangular binary-code train P2 is provided which consists of the second and the fourth phases and which are spaced by 90 from the first and the third phases, respectively (and are separated by 180 from each other). Similar to the embodiment of FIG. 6, the first demodulated rectangular binary-code train P1 is divided at gates G1 (41) and G2 (42) into two parallel rectangular binary-code trains P1(G1) and P2(G2), which are supplied through the respective integrating circuits 51 and 52 and read-out circuits 61 and 62 to a single combining circuit 71. The output of combining circuit 71 is supplied to the shaping circuit 81 to be regenerated there into a first shaped rectangular binary-code train PM1 consisting of the first and the third phases. The second demodulated rectangular binary-code train P2 is also divided (at gates G1 (131) and G2'l (132)) into two parallel rectangular binary-code trains P2(G1) and P2(G2), which are supplied through respective integrating circuits 53 and 54 and reading-out circuits 63 and 64 to a single combining circuit 72. The output of combining circuit 72 is supplied to a shaping circuit 82 to be regenerated there into a second shaped rectangular binary-code train PM2 consisting of the second and the fourth phases. It is to be noted that although the frequency detector 37 of FIG. 20` is supplied the first demodulated rectangular binary-code train P1, it may be supplied with the second demodulated rectangular binary-code train P2.

FIG. 21 illustrates another embodiment of this invention. This embodiment is similar to the embodiment of FIG. 19 except that it is adapted for the case of fourphase phase-demodulation. In FIG. 2l, a partial fourphase phase-demodulated wave having a duty factor of 50% is derived at gate G1' (i101) and is then divided at a four-phase phase-demodulator 141 into a first partial rectangular binary-code train P1(G1') (consisting of the first and the third phases) and a second rectangular binary-code train P2(G1) (consisting of the second and the fourth phases). Another partial four-phase phasemodulated wave having a duty factor of 50% is derived at the gate G2 (102) and is divided at another four-phase demodulator 142 into another first partial rectangular binary-code ytrain P1(G2') (consisting of the first and the third phases) and another second rectangular binary-code train P2(G2) (consisting of the second and the fourth phases). Similar to the embodiment of FIG. 20, first and second shaped rectangular binary-code trains PMI and PM2 are regenerated from the four parallel rectangular binary-code Vtrains through the respective integrating circuits 51-54, read-out circuits 61-64, combining circuits 71 and 72, and shaping circuits 81 and 82. Incidentally, it is possible in this embodiment and in the embodiment illustrated in FIG. 20, to use the clock frequency detector 37, gate control signal generator 38, pulse generator 39, and gates G3, G4, G and G6 as common elements for both the first and the second demodulated rectangular-code trains P1 and P2.

While we have described above the principles of our invention in connection with specific embodiments, it is to be clearly understood that this description is made only by way of example, and not as a limitation to the scope of our invention as set forth in the objects thereof and in the accompanying claims.

What is claimed is:

1. A rectangular code pulse regeneratonrcomprising:

a source of an input signal modulated with a modulating train of multi-phase rectangular binary-code pulses;

means for demodulating said multi-phase modulated input signal to produce a modulated rectangular binarycode pulse train;

means for translating a first portion of said demodulated pulse train into a plurality of control rectangular pulse trains; a first of said plurality of control pulse trains comprising a square-wave pulse train having successively different voltage pulses of which first alternate voltage pulses constitute identical square-wave voltage pulses, each of said first and second alternate square-wave voltage pulses occurring during the time interval of an elementary code of said demodulated binary-code pulse train; and a second of said plurality of control pulse trains comprising a rectangular pulse train synchronized with said demodulated binary-code pulse train, each of said second control pulses having a time duration shorter than one-half the time duration of said elementary code;

first and second gating means activated by said squarewave pulse trains and a second portion of said demodulated binary-code pulse train in such manner that said first gating means is opened in response to said first alternate square-wave pulse train to transmit rst alternate elementary codes of said demodulated binary-code pulse train therethrough to provide a first partial demodulated rectangular binary-code pulse train while said second gating means is closed and further in such manner that said second gating means is opened in response to said second alternate square-wave pulse train to transmit second alternate elementary codes of said demodulated binary-code pulse train therethrough to provide a second partial demodulated rectangular binary-code pulse train while said first gating means is closed;

first means for integrating said first partial demodulated binary-code pulse train to provide a first train of integrated pulses;

second means for integrating said second partial demodulated binary-code pulse train to provide a second train of integrated pulses;

third and fourth gating means activated by said sq-uare- Wave and second control rectangular pulse trains in such manner that said third gating means is closed during said first alternate square-wave voltage pulse train and is opened in response to said second alternate square-wave voltage and second control pulse trains for reading out said first integrated pulse train to provide a first train of read-out pulses and further in such manner that said fourth gating means is closed during said second alternate square-wave voltage pulse train and is opened in response to said first alternate square-wave voltage and second control pulse trains for reading out said second integrated pulse train to provide a second train of read-out pulses;

means for converting said first and second read-out pulse trains into a multi-phase rectangular binarycode pulse train as a replica of said train of multiphase rectangular binary-code pulses modulating said input signal;

and means for utilizing said replica multi-phase rectangular binary-code pulse train.

2. The regenerator according to claim 1 in which said plurality of control rectangular pulse trains includes a third rectangular pulse train lagging said second rectangular pulse train by a time duration equal to the time duration of each of said second control pulses, each of said third control pulses having a time duration equal to the time duration of each of said second control pulses;

and said regenerator also including fifth and sixth gating means responsive to said square-wave and third control pulse trains in such manner that said `fifth gating means is closed during said first alternate square-wave pulse train and is opened in response to said second alternate square-wave and third ycontrol pulse trains to discharge said first integrated pulse `train in said first integrating means and further in such manner that said sixt-h gating means is closed during said second alternate squarewave voltage pulse train and is opened in response to said first alternate square-wave and third control pulse trains to discharge said second integrated pulse train in said second integrating means.

3. A rectangular code pulse regenerator, comprising:

a source of an input signal modulated with a modulating Itrain of multi-phase rectangular Ibinary-code pulses;

means for demodulating said modulated input signal to produce a demodulated rectangular binary-'code pulse train;

means for translating a first portion of said demodulated pulse train into a plurality of control rectangular pulse trains; a first of said plurality of control pulse trains comprising a square-wave pulse train having successively different voltage pulses of which first alternate voltage pulses constitute identical square- Wave voltage pulses and second alternate voltage pulses constitute identical square-wave voltage pulses, each of said first and second alternate square-wave voltage pulses occurring during the time interval of an elementary code of said demodulated binarycode pulse train; a second of said plurality of control pulse trains comprising a rectangular pulse train synchronized with said demodulated binary-code pulse train, each of s-aid second control pulses having -a time duration shorter than one-half the time duration of said elementary code pulse; and a .third of said plurality of control pulse trains comprising a rectangular pulse train lagging said second control pulse train by a time duration equalnto the time duration of each of said second control pulses, each of said third control pulses having a time duration equal to the time duration of each of said second control pulses;

first and second gating means activated by said squarewave pulse trains and a second portion of said demodulated binary-code pulse train in such manner 'that said first gating means is opened in response to said first alternate square-Wave pulse train to transmit first alternate elementary codes of said demodulated binary-code pulse train therethrough to provide a first partial demodulated rectangular binarycode pulse train While said second gating means is closed and further in such manner that said second gating means is opened in response to said second alternate square-wave pulse train to transmit -second alternate elementary codes of said demodulated binary-code pulse t-rain therethrough to provide a second partial demodulated rectangular binary-code pulse train while said first gating means is closed;

first means for integrating said first partial demodulated binary-code pulse train to provide a first train of integrated pulses;

second means for integrating said second partial demodulated binary-code pulse train to provide a second train of integrated pulses;

third and fourth gating means responsive to said square-Wave pulse trains and second and .third control pulse trains in such manner that said third and fourth gat-ing means are closed during said first alternate square-wave voltage pulse train while said first integrating means is integrating said first par-tial demodulated binary-code pulse train and further in such manner that said third gating means is opened in response to said second alternate square-wave and second control pulse trains to read-out said first integrated pulse train to provide a first train of readout pulses and said fourth gating means is opened in response to said second alternate square-Wave and third control pulse trains `to discharge said first integrated pulse train in said first integrating means;

fifth and sixth gating means responsive to said squarewave pulse trains and second and third control pulse trains in such manner that said fifth and sixth gating means are closed during said secondalternate squarewave voltage train While said second integrating means is integrating said second partial demodulated Ibinary-code pulse train and further in such manner that said fifth gating means is opened in response to said first alternate square-wave voltage and second control pulse trains -to read-out said second integrated pulse train to provide -a second train of readout pulses and said sixth gating means is opened in response to said first alternate square-wave and third control pulse trains to ydischarge said second integrated pulse train in said second integrating means;

means for converting said first and second read-out pulse trains into a multi-phase rectangular binarycode pulse train as a replica of said multi-phase rectangular Ibinary-code pulse train modulating said input signal;

and means for utilizing said replica multi-phase rectangular binary-code pulse train.

4. A rectangular code pulse regenerator, comprising:

a source of an input signal modulated with a modulating t'rain of two-phase rectangular binary-code pulses;

first Ameans for demodulating a first portion of said modulated input signal to produce a demodulated rectangular binary-code pulse train;

means for translating said ldemodulated binary-code pulse train into a plurality of control rectangular pulse trains; a first of said plurality of control pulse trains comprising a square-wave pulse train having successively different voltage pulses of which first alternate voltage pulses constitute identical square- Wave voltage pulses and second alternate 'voltage pulses constitute identical square-wave voltage pulses, each of said first and second alternate square- Wave voltage pulses occurring during the time interval of an elementary code of said demodulated binary-code pulse train; and a second of said plurality of control pulse trains comprising a rectangular pulse train synchronized with said demodulated binary-code pulse train, each of said second control pulses having a time duration shorter than one-half the time duration of said elementary code;

first and second gating means activated by said squarewave pulse trains and a second portion of said modulated input signal in such manner that said `first gating means is opened in response to said first alternate square-wave pulse train to transmit a train of first alternate elementary codes of said modulated input signal While said second gating means is closed and further in such manner that said second gating means is opened in response to said second alternate squarewave pulse train to transmit a train :of second alternate elementary codes of said modulated input signal therethrough to provide a second partial modulated rectangular binary-code pulse train of said modulated input signal while said first gating means is closed;

second means for demodulating said first partial modulated binary-code pulse train to provide a first partial demodulated rectangular binary-code pulse train;

third means for demodulating said second partial modulated binary-code pulse train to provide a second partial demodulated rectangular binary-code pulse train;

first means for integrating said first partial demodulated binary-code pulse train to provide a first train of integrated pulses;

third and fourth gating means actuated by said squarewave and second control pulse trains in such manner that third gating means is closed during said -frst alternate square-wave voltage pulse train and is opened in response to said second alternate squarewave voltage and second control pulse trains for reading out said first integrated pulse train to provide a first train of read-out pulses and further in such manner that said fourth gating means is closed during said second alternate square-Wave voltage pulse train and is opened in response to said first alternate square-wave voltage and second control pulse trains 1 1 for reading out said second integrated pulse train to provide a second train of read-out pulses;

means for converting said first and second read-out pulse trains into a two-phase rectangular binarycode pulse train as a replica of said train of twophase binary code pulses modulating said input signal; and means for utilizing said replica two-phase rectangular binary-code pulse train. l 5. The regenerator according to claim 4 in which said plurality of control rectangular pulse trains includes a third rectangular pulse train lagging said second control pulse train by a time duration equal to the time duration of each of said second control pulses, each of said third control pulses having a time duration equal to the time duration of each of said second control pulses;

and said regenerator also including fifth and sixth gating means responsive to said square-Wave and third control pulse trains in such manner that said fifth gating means is closed during said first alternate squarewave pulse train and is opened in response to said second alternate square-wave and third control pulse trains to discharge said first integrated pulse train in said first integrating means and further in such manner that said sixth gating means is closed during said second alternate square-Wave pulse train and is opened in response to said first alternate square-wave and third control pulse trains to discharge said second integrated pulse train in said second integrating means.

6. A rectangular code pulse regenerator, comprising: a source of an input signal modulated with a modulating train of two-phase rectangular binary-code pulses; means for demodulating a first portion `of said modulated input signal to produce a demodulated rectangular binary-code pulse train; means for translating said demodulated binary-code pulse train into a plurality of control rectangular pulse trains; a `first of said control pulse trains comprising a square-wave pulse train having successively different voltage pulses of which first alternate volt- :age pulses constitute identical square-wave voltage pulses and second alternate voltage pulses constitute identical square-wave voltage pulses, each of said first and second alternate square-Wave voltage pulses 1 occurring during the time interval of an elementary code of said demodulated binary-code pulse train; a second of said plurality of control pulse trains comprising a rectangular pulse train synchronized With said demodulated binary-code pulse train, each of said y second control pulses having the time duration shorter than one-half the time duration of said elementary code; and a third of said plurality of control pulse trains comprising a rectangular pulse train lagging said second control pulse train by a time duration equal to the time duration of each of said second control pulses, each of said third control pulses having a time duration equal to the time duration of each of said second control pulses;

first and second gating means actuated by said squarewave pulse trains and a second portion of said modulated input signal in such manner that said first gating means is opened to transmit a train of first alternate elementary codes of said modulated input signal therethrough to provide a first partial modulated rectangular binary-code pulse train of said modulated input signal while said gating means is closed and further in such manner that said second gating means 1s opened to transmit a train of second alternate elementary codes of said modulated input signal therethrough to provide a second partial demodulated rectangular binary-code pulse train of said modulated input signal while said first gating means is closed; second means for demodulating said first partial modulated binary-code pulse train to provide a first partial demodulated rectangular binary-code pulse train;

third lmeans for demodulating said second partial modulated binary-code pulse train to provide a second partial demodulated rectangular binary-code pulse train;

first means for integrating said first partial demodulated binary-code pulse train to provide a first train of integrated pulses;

second means for integrating said second partial demodulated binary-code pulse train to provide a second train of integrated pulses;

third and fourth gating means actuated by said squarewave and second and third control pulse trains in such manner that said third and fourth gating means are closed in response to said first alternate squarewave pulse train while said first integrating means is integrating said first partial demodulated binary-code pulse train and further in such manner that said third gating means is opened in response to said second alternate square-wave and second control pulse trains to read-out said rst integrated pulse train to provide a first train of read-out pulses and said fourth gating means is opened in response to said alternate squarewave and third control pulse trains to discharge said first integrated pulse train in said first integrating means;

fifth and sixth gating means activated by said squarewave and second and third control pulse trains in such manner that said fifth and sixth gating means are closed in response to said second alternate squarewave pulse train while said second integrating means is integrating said second partial demodulated binarycode pulse train and further in such manner that said fifth gating means is opened in response to said first alternate square-wave and second control pulse trains to read-out said second integrated pulse train to provide a second train of read-out pulses and said sixth gating means is opened in response to said first alternate square-wave and third control pulse trains to discharge said second integrated pulse train in said second integrating means;

means for converting said first and second read-out pulse trains into a two-phase rectangular binary-code pulse train as a replica of said two-phase rectangular binary-code pulse train modulating said input signal; and

means for utilizing said replica two-phase rectangular binary-code pulse train.

7. A rectangular pulse train regenerator, comprising:

a source of an input signal four-phase modulated with two modulating trains of different two-phase rectangular binary-code pulses;

means for demodulating said two different two-phase modulated input signal to provide a first demodulated rectangular binary-code pulse train including first and third phases separated by 180 from each other and a second demodulated rectangular binarycode pulse train including second and fourth phases separated by 180 from each other, said first and third phases separated from said second and fourth phases by means for translating a first portion of said first demodulated pulse train into a plurality of control rectangular pulse trains; a first of said control pulse trains comprising a square-wave pulse train having successively different voltage pulses of which first alternate voltage pulses constitute identical squarewave voltage pulses, each of said first and second alternate square-wave voltage pulses occurring during the time interval of an elementary code of said first demodulated rectangular binary-code pulse train; and

a second of said plurality of control pulse trains comprising a rectangular pulse train synchronized with said first demodulated pulse train, each of said second control pulses having a time duration shorter than one-half the time duration of said elementary code;

first and second gating means activated by said squarewave control pulse trains and a second portion of said first demodulated pulse train in such manner that said first gating means is opened in response to lsaid first alternate square-wave pulse train for transmitting first alternate elementary codes of said lastrnentioned demodulated pulse train therethrough to provide .a first partial demodulated pulse train of said last-mentioned demodulated pulse train while said second gating means is closed and further in such manner that said second gating means is opened in response to said second alternate square-wave pulse train for transmitting second alternate elementary codes of said first demodulated pulse train therethrough to provide a second partial demodulated pulse train of said last-mentioned demodulated pulse train while said first gating means is closed;

third and fourth gating means activated by said squarewave control pulse trains and second demodulated pulse train in such manner that said third gating means is opened in response to said first alternate square-wave pulse train for transmitting first alternate elementary codes of said last-mentioned demodulated pulse train therethrough to provide a first partial demodulated pulse train of said last-mentioned demodulated pulse train when said fourth gating means is closed and further in such manner that said fourth gating means is opened in response to said alternate square-Wave pulse train for transmitting second alternate elementary codes of said second demodulated pulse train therethrough to provide a second partial demodulated pulse train of said lastmentioned demodulated pulse train while said third gating means is closed;

first means for integrating said first partial demodulated pulse train of said first demodulated pulse train to provide a first train of integrated pulses;

second means for integrating said first partial demodulated pulse train to provide a second train of integrated pulses;

third means for integrating said second partial demodulated pulse train of said first demodulated pulse train to provide a third train of integrated pulses;

fourth means for integrating said second partial demodulated pulse train of said second demodulated pulse train to provide a fourth train of integrated pulses;

fifth and sixth gating means activated by said squarewave and second control pulse trains in such manner that fifth gating means is closed during said first alternate square-wave pulse train and is opened in response to said second square-wave and second control pulse trains for reading out said first and second integrated pulse trains to provide first and second discrete read-out pulse trains, respectively, and further in such manner that said sixth gating means is closed during said second alternate square-wave pulse train and is opened in response to said first alternate square-wave and second control pulse trains for reading out said third and fourth integrated pulse trains to provide third and fourth discrete read-out pulse trains, respectively;

means for converting said first and third read-out pulse trains into a two-phase rectangular binary-code pulse train as a replica of one of said two two-phase rectangular binary-code pulse trains modulatingl said input signal and including first and third phases;

means for converting said second and fourth read-out pulse trains into a two-phase rectangular binary-code pulse train as a replica of the other of said two twophase rectangular binary-code pulse trains modulating said input signal and including second and fourthphases;

and means for utilizing said first and second-mentioned replica pulse trains.

8. The regenerator according to claim 7 in which said plurality of control rectangular pulse trains includes a third rectangular pulse train lagging said second control rectangular pulse train by a time duration equal to the time duration of code of said second control pulses, each of said third control pulses having a time duration equal to the time duration of each of said second control pulses; and

said regenerator also including seventh and eighth gating means activated by said square-wave and third control pulse trains in such manner that said seventh gating means is closed during said first alternate square-Wave pulse train and is opened in response to said second alternate square-wave and third control pulse trains to discharge said first and second integrated pulse trains in said first and second integrating means, respectively, and further in such manner that said eighth gating means is closed during said second alternate square-wave pulse train and is opened in response to said first alternate square-wave and third control pulse trains to discharge said third and fourth integrated pulse trains in said third and fourth integrating means, respectively. 9. A rectangular pulse train regenerator, comprising:v a source of an input signal four-phase modulated with two modulating trains of different two-phase rectangular binary-code pulses; means for demodulating said two different two-phase modulated input signal to provide a first demodulated rectangular binary-code pulse train including first and third phases separated by 180 from each other and a second demodulated rectangular rbinary-code pulse train including second and fourth phases separated by 180 from each other, said first and third phases separated by from said second and fourth phases; means for translating a first portion of said first demodulated pulse train into a plurality of control rectangular pulse trains; a first of said control pulse trains comprising a square-wave pulse train having successively different voltage pulses of which first alternate square- Wave pulses constitute identical pulses and second alternate square-wave pulses constitute identical pulses, each of said first and second alternate squarewave pulses occurring during the time interval of an elementary code of said first demodulated pulse train; a second of said plurality of control pulse trains cornprising a rectangular pulse train synchronized with said last-mentioned first demodulated pulse train, each of said second control pulses having a time duration shorter than one-half the time duration of said elementary code; and a third of said plurality of control pulse trains comprising a rectangular pulse train lagging said second control pulse train by a time `duration equal to the time duration of each of said second control pulses, each 4of said third control pulses having a time duration equal to the time duration of each of said second control pulses, each of said third `control pulses having a time duration equal to the time duration of each of said second control pulses; first and second gating means activated by said square- `wave control pulse trains and a second portion of said first demodulated pulse train in such manner that said first gating means is opened in response to said first alternate square-wave pulse train for transmitting first alternate elementary codes of said last-mentioned demodulated pulse train therethrough to provide a first partial demodulated pulse train of said lastmentioned first demodulated pulse train while said second gating means is closed and further in such manner that said second gating means is opened in 15 response to said second alternate square-wave pulse train for transmitting second alternate elementary codes of said last-mentioned first demodulated pulse trains therethrough to provide a second partial demodualted pulse train of said last-mentioned first' demodulated pulse train while said first gating means is closed;

third and fourth gating means activated by said square- Wave pulse trains and second demodulated pulse train in such manner that said third gating means is opened in response to said first alternate square-wave pulse train for transmitting first alternate elementary codes of said last-mentioned second demodulated pulse train therethrough to provide a first partial demodulated pulse train of said last-mentioned second demodulated pulse train while said fourth gating means is closed and further in such manner that said fourth gating means is opened in response to said second alternate square-wave pulse train for transmitting second alternate elementary codes of said last-mentioned second demodulated pulse train therethrough to provide a second partial demodulated pulse train of said last-mentioned second demodulated pulse train While said third gating means is closed;

first means for integrating said first par-tial demodulated pulse train of said first demodulated pulse train to provide a first train of integrated pulses;

second means for integrating said first partial demodulated pulse train of said second demodulated pulse train to provide a second train of integrated pulses;

third means for integrating said second partial demodulated pulse train of said first demodulated pulse train to provide a third train of integrated pulses;

fourth means for integrating said second partial demodulated pulse train of said second demodulated pulse train to provide a fourth train of integrated pulses;

fifth and sixth gating means activated by said squarewave pulse trains and second and third control pulse trains in such manner that said fifth and sixth gating means are closed during said first alternate square- Wave pulse train and further in such manner that said fifth gating means is opened in response to said second alternate square-wave and second control pulse trains for reading out said first and second integrated pulse trains as first and second discrete read-out pulse trains, respectively, and said sixth gating means is opened in response to said second lalternate square-wave and third control pulse trains to discharge said first and second integrated pulse trains in said first and second integrating means, respectively;

seventh and eighth gating means activated by said square-wave pulse trains and second and third control pulse trains in `such manner that seven-th and eighth gating means are closed during said second alternate square-wave pulse train and further in such manner that seventh gating means is opened in response to said first alternate square-Wave and second control pulse trains for reading out said third and fourth integrated pulse trains as third and fourth discrete read-out pulse trains, respectively, and said eighth gating means is opened in response to said first alternate square-wave and third control pulse trains to discharge said third and fourth integrated pulse trains in said third and fourth integrating means, respectively;

means for converting said first and third read-out pulse trains into a two-phase rectangular binary-code pulse train as a replica of one of said two two-phase rectangular binary-code pulse trains modulating said input signal and including first and third phases;

means for converting said second and fourth read-out pulse trains into a two-phase rectangular binary-code pulse train as a replica of the other of said two twophase rectangular binary-code pulse trains modulating said input signal and including second and fourth phases; and

means for utilizing said first and second-mentioned replica pulse trains.

10. A rectangular pulse Vtrain regenerator, comprising:

a source of aninput signal four-phase modulated by two modulating trains of different two-phase rectangular binary-code pulses;

first means for demodulating said input signal as modulated with one of said two two-phase modulating signals to provide a first demodulated rectangular binary-code pulse train including first and third phases separated from each other by 180;

means for translating said first demodulated pulse train into 'a plurality of control rectangular pulse trains; a Lfirst of said control pulse trains comprising a square- Wave pulse train having successively different voltage pulses of which first alternate voltage pulses constitute identical square-wave voltage pulses, each of said first and second square-Wave pulses occurring during the time interval of an elementary code of said first demodulated pulse train; and a second of said plurality of control pulse trains comprising a rectangular pulse train synchronized with said first demodulated pulse train, each of said second control pulses having a time duration shorter than one-half 4the time duration of said elementary code;

first and second gating means activated by said squarewave pulse trains and four-phase modulated input signal in such manner that said first gating means is opened in response to said first alternate squarewave pulse train to transmit first alternate elementary codes of said four-phase modulated input signal therethrough to provide a first partial train of said last-mentioned four-phase modulated input signal while said second gating means is closed and further in such manner that said second gating means is opened in response to said second alternate square- Wave pulse train to transmit second alternate elementary codes of said four-phase modulated input signal therethrough to provide a second partial train of said last-mentioned four-phase modulated input signal while said first gating means is closed;

secondmeans for demodulating said first partial train of said four-phase input signal to provide a first partial demodulated rectangular binary-code pulse train having said first and third phases separated by 180 and a second partial demodulated rectangular binarycode pulse train having second and fourth phases separated from each other by 180; said first and third phases separated from said second and fourth phases by second means for demodulating said second partial train of said four-phase input signal to provide a third partial demodulated rectangular binary-code pulse trains having said first and third phases and a fourth partial demodulated rectangular binarycode pulse train having said second and fourth phases;

first means for integrating said first partial demodulated pulse train to provide a first train of integrated pulses;

second means for integrating said second partial demodulated pulse train to provide a second train of integrated pulses;

third means for integrating said third partial demodulated pulse train to provide a third train of integrated pulses;

fourth means for integrating said fourth partial demodulated pulse train to provide a fourth train of integrated pulses;

third and fourth gating means activated by said squarewave and second control pulse trains in such manner that said third gating means is closed during said first alternate squarewave .pulse train and is opened in response to said second alternate squarewave and second control pulse trains for reading out said first and second integrated pulse trains to provide first and second discrete read-out pulse trains, respectively, and furtherin such manner that said fourth gating means is closed during said second alternate squarewave pulse train and is opened in response Ato said first alternate squarewave and second control pulse trains for reading out said third and fourth integrated pulse trains to provide third and fourth discrete read-out pulse trains, respective- 1y;

means for converting said first and third read-out pulse trains into a two-phase rectangular binary-code pulse train having said first and third phases as a replica of said one two-phase modulating pulse train having first and third phases;

means for converting said second land fourth read-out pulse trains into a two-phase rectangular binarycode pulse train having said second and fourth phases as a replica of the other of said two twophase modulating pulse trains having second and fourth phases; and

means for utilizing said first and second-mentioned replica pulse trains.

11. The regenerator according to claim I in which said plurality of control rectangular pulse trains includes a third rectangular pulse train lagging said second rectangular pulse train by a time duration equal to the time duration of each of said second control pulses, each third control pulses having a time duration equal to the time duration of each of said second control pulses;

said regenerator also including fifth and sixth gating means activated by said square-wave and third control pulse trains in such Imanner that said fifth gating means is closed during said first alternate square-wave pulse train and is opened in response to said second alternate squarewave and third control pulse trains to discharge said first and second integrated pulse trains in said first and second integration means, respectively, and further in such manner that sixth gating means is closed during said second alternate square-wave -pulse train and is opened in responsey to said first alternate squarewave and third control pulse trains to discharge said third and fourth :integrated pulse trains in said third and fourth integrating means, respectively.

12. A rectangular pulse train regenerator, comprismg:

a source of an input signal four-phase modulated with two modulating trains of different two-phase rectangular binary-code'pulses; first means for demodulating said input signal as modulated with one of said two two-phase rectangular :binary-code pulse trains to produce a first demodulated rectangular binary-code pulse train including first and third phases separated from each other by 180;

means for translating said first demodulated pulse train into a plurality of control rectangular pulse trains;

a first of said control pulse trains comprising a square-wave pulse train having successively different voltage pulses of which first alternate voltage pulses constitute identical square-wave voltage pulses and second alternate voltage pulses constitute identical square-wave voltage pulses, each of said first and second square-wave pulses occurring during the time interval of an elementary code of said first demodulated pulse train; a second of said plurality of control pulse trains comprising rectangular pulse train synchronized with said first demodulated pulse train, each of said second control pulses having a time duration shorter than one-half the time duration of 18 said elementary code;`and a third of said plurality of control pulse trains including a third rectangular pulse train lagging said second rectangular pulse train by a time duration equal to the time duration of each of said second control pulses, each of said third control pulses having a time duration equal to the time duration of each of said second control pulses.

first and second gating means activated by said squarewave pulse 4trains and four-phase modulated input signal in such manner that said first gating means is opened in response to said first alternate'square-wave pulse train to transmit first alternate elementary codes of said four-phase modulated input signal therethrough to provide a first partial train of said lastmentioned four-phase modulated inputl signal while said second gating means is closed and further in such manner that said second gating means is opened in response to said second alternate square-wave pulse train to transmit second alternate elementary codes of said four-phase modulated input signal therethrough to provide a second partial train of said lastmentioned four-phase modulated input signal while said first gating means is closed;

second means for demodulating said first partial train of said four-phase modulated input signal to produce a first partial demodulated rectangular binary-code pulse train including said first and third phases and a second partial demodulated rectangular binary-code pulse train including second and fourth phases separated from each other by 180; said first and third phases separated from said second and fourth phases by third means for demodulating said second partial train of said four-phase modulated input signal to produce a third partial demodulated rectangular binary-code pulse train including said first and third phases and a fourth partial demodulated rectangular binary-code pulse train including said second and fourth phases;

first means for integrating said first partial demodulated pulse train to provide a first train of integrated pulses;

second means for integrating said second partial demodulated pulse train to provide a second train of integrated pulses;

third means for integrating said third partial demodulated pulse train to provide a third train of integrated pulses;

fourth means for integrating said fourth partial demodulated pulse train to provide a fourth train of integrated pulses;

third and fourth gating means activated by said squarewave and second and third control pulse trains in such manner that third and fourth gating means are closed during said first alternate square-wave pulse train and further in such manner that third gating means is opened in response to said second alternate square-wave and second control pulse trains td readout said first and second integrated pulse trains as first and second discrete read-out pulse trains, respectively, and said fourth gating means is opened in response to said second alternate square wave and third control pulse trains to discharge said first and second integrated pulse trains in said first and second integrating means, respectively;

Y fifth and sixth means activated by said square-wave and second and third pulse trains in such manner that said fifth and sixth gating means are closed during said second alternate square-wave pulse train and further in such manner that said fifth gating means is opened in response to said first alternate square-wave and second control pulse trains to read-out said third and fourth discrete read-out pulse trains, respectively, and said sixth gating means is opened in response to said first alternate square-wave and third control pulse trains to discharge said third and fourth integrated pulse trains in said third and fourth integrating means, respectively;

means for converting said first and third read-out pulse trains into a two-phase rectangular binary-code pulse train including rst and third phases as a replica of said one modulating two-phase rectangular binarycode pulse train including said rst and third phases;

means for converting said second and fourth read-out pulse trains into a two-phase rectangular binarycode pulse train including second and fourth phases as a replica of the other of said two two-phase rectangular binary-code pulse trains including second and fourth phases; and

means for utilizing said first and second-mentioned replica pulse trains..

References Cited Crafts et al 329-105 ROBERT L. GRIFFIN, Prmry Examiner.

10 A. H. EDDLEMAN, Assistant Examiner.

U.S. Cl. X.R. 

